1. Field of the Invention
The present invention generally relates to a wiring layer dry etching method. More particularly, the invention relates to a wiring layer dry etching method improved in that in the processing of a multilayer wiring of, for example, gate electrode, Al, and Cu layers, or in the forming of a plug according to an overall-surface etch back method, a high selectivity to a base is maintained, and the occurrence of etch residues is suppressed. The method thereby enables the provision of a semiconductor device that has high reliability and that does not cause electrical short circuiting. Furthermore, the invention relates to a semiconductor device manufacturing method including steps of the wiring layer dry etching method.
2. Description of the Background Art
Referring to FIGS. 5 to 7, a description will be made regarding a conventional processing method for a polysilicon gate electrode.
FIG. 5 is a schematic view showing the flow of oxygen in the vicinity of a wafer and in a chamber at the time of breakthrough (discharging). FIG. 6 is a schematic view showing the flow of oxygen in the vicinity of a wafer and in a chamber at the time of interstep vacuuming (discharge termination). FIG. 7 is a schematic view showing a conventional wiring layer dry etching method.
Referring to FIG. 5, on a silicon substrate 7, there are sequentially formed a gate insulation film 8, a polysilicon layer 9 used as a gate electrode material, and a silicon oxide film 10 and a resist film (not shown) used as masks during the processing of the gate electrode. FIG. 5 illustrates a semiconductor device in a state where silicon oxide film 10 was etched by using a resist as a mask, polysilicon was exposed, and then, the resist was removed.
Silicon substrate 7 is disposed in a reaction chamber 1. Reaction chamber 1 includes quartz members 2, and is connected to a vacuum pump 4 via a conductance valve 3. In reaction chamber 1, a reactive ion 5 is generated, and residual oxygen 6 remains.
An etching gas used for silicon oxide film 10 includes at least one of CHF3, CH2F2, CF4, C2F6, c-C4F8, c-C5F8, and C4F6. The etching gas also includes at least one of O2, CO, CO2, H2O , and N2; and at least one of Ar, He, and Xe. For example, one of mixed gases CHF3/O2/Ar, CHF3/CF4/Ar, C4F8/O2/Ar, C5F8/O2/Ar, or C4F6/O2/Ar is used for the etching gas.
Subsequently, polysilicon layer 9 is etched using silicon oxide film 10 as a mask, and the etching is stopped on gate insulation film 8 (base). After the etching of the silicon oxide film 10 is performed, affected layers (such as a natural oxide film layer, a SiC layer, and a fluorocarbon polymer layer) are formed on the surface of polysilicon layer 9.
To etch polysilicon layer 9, the method performs three steps as described below. As the first step, the method removes affected layers in a step (breakthrough step; the step will be referred to as a xe2x80x9cBT stepxe2x80x9d in the present Specification) for which the selectivity to Si/SiO2 is set to be relatively low (selectivity: 0.8 to 10). In this step, the method uses an etching gas including at least Cl2, for example, Cl2, Cl2/O2, Cl2/CF4, Cl2/SF6, or Cl2/HBr. HBr/O2 may also be used.
As the second step, the method performs a step (polysilicon main etching step; the step will be referred to as an xe2x80x9cME stepxe2x80x9d in the present Specification) for which the selectivity to Si/SiO2 is set to be relatively high (selectivity: 10 to 40). In this step, the method uses an etching gas, for example, Cl2, Cl2/O2, Cl2/HBr, or Cl2/HBr/O2. Since the selectivity to Si/SiO2 increases in proportion to an increase in the flow ratio of O2 to Cl2, an O2 flow ratio in the ME step is set higher than that in the BT step. However, preferably, either in the BT step or the MT step, the O2 flow ratio is set below 20% of the total mass-flow rate. This is because, with the O2 flow ratio higher than 20%, since the surface of the polysilicon layer progresses, etch residues increase; or alternatively, etching does not progress and terminates.
As the third step, when the selectivity to a base is insufficient, the step needs to be shifted to a step (overetching step, which will be referred to as an xe2x80x9cOE stepxe2x80x9d in this Specification) of which selectivity is higher (selectivity: 20 to 100) than that in the ME step, at the same time when gate insulation film 8 is exposed or immediately before the gate insulation film 8 is exposed. For an etching gas, Cl2/O2, Cl2/HBr, Cl2/HBr/O2, or HBr/O2 is used. In this case, however, the O2 flow ratio is preferably set higher than or equal to that in the ME step.
Generally, in the ME step, discharge is started after termination of discharge between the BT step and the ME step. In addition, gas vacuuming is performed to stabilize the gas flow rate and pressure that are set at the subsequent ME step.
However, referring to FIG. 6, in reaction chamber 1 where many quartz members 2 are used, oxygen is discharged from quartz members 2 because of sputtering at the BT step. In addition, in the case where O2 is included in gases at the BT step, even in the condition where vacuuming has been performed, the polysilicon surface cleaned at the BT step is oxidized because of residual oxygen. That is, since discharge is stopped, the wafer surface is not sputtered and is therefore oxidized.
Hereinbelow, referring to FIG. 7, after the execution of the ME step in which the selectivity to Si/SiO2 is set to be relatively high, the etching of oxidized surface regions is delayed. Consequently, etching uniformity that can be achieved in the ME step is reduced.
The above causes problems in that etch residues are formed, thereby causing interwiring short circuiting. When the amount of etching is increased to prevent the interwiring short circuiting, however, pass-through is caused in a gate oxide film (base), silicon substrate 7 is thereby damaged. Consequently, electrical characteristics are reduced.
In addition, when ON/OFF discharges occur between the ME step and the OE step (that is, when a gate insulation film begins to be exposed), a problem is caused in that plasma is momentarily formed uneven, and charge-up-attributed damage to gate insulation film 8 is increased.
The present invention is made to solve the above-described problems, and an object thereof is to provide a wiring layer dry etching method improved not to damage a silicon substrate.
Another object of the present invention is to provide a wiring layer dry etching method improved not to reduce electrical characteristics.
Still another object of the present invention is to provide a wiring layer dry etching method improved not to cause charge-up attributed damage to a gate insulation film.
Still another object of the present invention is to provide a semiconductor device manufacturing method including one of the aforementioned wiring layer dry etching methods.
In a wiring layer dry etching method according to the first aspect of the present invention, first, a semiconductor substrate on which a mask for patterning a wiring layer is formed is prepared, in which the mask is formed on the wiring layer (first step). Affected layers on a surface of the wiring layer are dry-etched and removed (second step: BT step). The wiring layer is dry-etched by using the mask (third step: ME step). When shifting is performed from the BT step to the ME step, vacuuming is not performed, and continuous discharge is performed.
In a wiring layer dry etching method according to the second aspect of the present invention, first, a semiconductor substrate on which a mask for patterning a wiring layer is formed is prepared, in which the mask is formed on the wiring layer (first step). Affected layers on a surface of the wiring layer are dry-etched (second step: BT step). After the BT step, the wiring layer is dry-etched by using the mask (third step: ME step). The wiring layer is overetched under the condition of a high selectivity to a base region when the base region of the wiring layer begins to be exposed or before the base region thereof is exposed (fourth step: OE step). When shifting is performed from the BT step to the ME step and/or when shifting is performed from the ME step to the OE step, vacuuming is not performed, and continuous discharge is performed.
In the wiring layer dry etching method according to the third aspect of the present invention, first, a semiconductor substrate on which a mask for patterning a wiring layer is formed is prepared, in which the mask is formed on the wiring layer (first step). The wiring layer is dry-etched by using the mask (second step: ME step). The wiring layer is overetched under the condition of a high selectivity to a base region when the base region of the wiring layer begins to be exposed or before the base region thereof is exposed (third step: OE step). When shifting is performed from the BT step to the ME step and/or when shifting is performed from the ME step to the OE step, vacuuming is not performed, and continuous discharge is performed.
In addition, in the wiring layer dry etching method according to the fourth aspect of the present invention, preferably, at least one of the BT step, the ME step, and the OE step is performed by using an etching gas including Cl2 and/or HBr.
The above-described wiring layer dry etching method according to the fifth aspect of the present invention is preferably arranged as follows. The BT step is performed by using a pure Cl2 gas, a Cl2/O2 mixed gas or Cl2/F containing gas, the ME step is performed by using a pure Cl2 gas or a Cl2/O2 mixed gas, and the difference in total gas flow rates in the BT step and the ME step is controlled to be lower or equal to xc2x150%. An O2 flow ratio in the ME step is controlled to be higher than that in the BT step. Concurrently, the O2 flow ratio in each of the BT step and the ME step is controlled not to exceed 20% of the total gas flow rate. The Cl2/F containing gas includes Cl2/CF4, Cl2/O2/CF4, Cl2/CHF3, Cl2/O2/CHF3, Cl2/SF6, or Cl2/O2/SF6 
The above-described wiring layer dry etching method according to the sixth aspect of the present invention is preferably arranged as follows. The BT step is performed by using a gas including one of a pure Cl2, a Cl2/O2 mixed gas, a Cl2/HBr/O2 mixed gas, an HBr/Cl2 mixed gas, and an HBr/O2 mixed gas. Each of the ME step and the OE step is performed by using a gas including one of Cl2/O2, Cl2/HBr/O2, HBr/Cl2, and HBr/O2. The difference in total gas flow rates in the BT step, the ME step, and the OE step is controlled to be lower or equal to xc2x150%. An O2 flow ratio in the ME step is controlled to be higher than that in the BT step. Concurrently, the O2 flow ratio in each of the BT step or the ME step is controlled not to exceed 20% of the total gas flow rate.
In addition, the wiring layer dry etching method according to the seventh aspect of the invention is preferably arranged as follows. The BT step is performed by using one of a pure Cl2 gas and a Cl2/HBr mixed gas. The ME step is performed by using a gas including Cl2/HBr/O2. The difference in total gas flow rates in the BT step, the ME step, and the OE step is controlled to be lower or equal to xc2x150%.
Furthermore, the wiring layer dry etching method according to the eighth aspect of the present invention is preferably arranged as follows. The BT step is performed by using a pure Cl2 gas or a Cl2/O2 gas. The ME step is performed by using a gas including Cl2/O2. The OE step is performed by using a gas including an HBr/O2 gas. The difference in total gas flow rates in the BT step and the ME step is controlled to be lower or equal to xc2x150%. An O2 flow ratio in the ME step is controlled to be higher than that in the BT step, and concurrently, the O2 flow ratio in each of the BT step or the ME step is controlled not to exceed 20% of the total gas flow rate. In addition, at least one step using a gas including Cl2/HBr/O2 is performed between the ME step and the OE step.
The above-described wiring layer dry etching method according to the ninth aspect of the present invention may be arranged as follows. The BT step is performed by using one of a pure Cl2 gas and a Cl2/BCl3 mixed gas. The ME step is performed by using a gas including Cl2/BCl3. The difference in total gas flow rates in the BT step and the ME step is controlled to be lower or equal to xc2x150%. The gas including Cl2 or Cl2/BCl3 includes a pure Cl2 gas, a Cl2/BCl3 mixed gas, Cl2/BCl3/Ar or Cl2/BCl3/CHF3.
In addition, the wiring layer dry etching method according to the tenth aspect of the present invention is preferably arranged such that at least one step of entering a mixed gas including a reducing gas is performed when shifting is performed for each of the BT step and the ME step.
In the wiring layer dry etching method according to the eleventh aspect of the present invention, the wiring layer preferably includes one of polysilicon, WSi/polysilicon, W/polysilicon, W, Ru, Pt, Ir, Ti, TiN, TiW, Al, AlSi, AlSiCu, AlCu, Ta, and TaN. In addition, the polysilicon preferably includes amorphous silicon or doped silicon.
In a wiring layer dry etching method according to the twelfth aspect of the present invention, first, a semiconductor substrate on which a mask for patterning a wiring layer is formed is prepared, in which the mask is formed on the wiring layer. Affected layers on a surface of the wiring layer are dry-etched and removed (BT step). The wiring layer is dry-etched by using the mask (ME step). When shifting is performed from the BT step to the ME step, vacuuming is not performed, and continuous discharge is performed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.